Memory
The memory module has 64 KB of addressable memory space with a base configuration of 16 KB of ROM and 48 KB of RAM. Bank switching is supported extending the available memory to
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128 KB of RAM (with extension)
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16 KB of system ROM
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16 KB of cartridge ROM
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16 KB of BASIC ROM (extension)
-
16 KB of extra ROM (extension via IO board)
Memory Control
Four control signals control the operation of the general purpose register.
RD |
Active high |
Memory read from the address on the address bus to the data bus |
|---|---|---|
WR |
Active high |
Write the contents of the data bus to the address on asserted to the address bus |
MEMRQ |
Active high |
A memory operation is occurring and the memory module has authority on the address and data buses |
BANK |
Active high |
Write the contents data bus to the bank register |
Banking
In this description logical banks in the memory map are referred to with the letters A, B, C and D. These banks are what the CPU sees and addresses. The physical memory that a bank refers to can be changed via the bank register. These physical memory areas are called blocks and are referred to with numbers 1, 2, 3, …. For example, Bank A:0 refers to the A bank set to the first block of ROM. Similarly, D:3 refers to the D bank set to the fourth block of RAM in the memory expansion board.
| H Addr | L Addr | Decimal | Bank | Addr Size |
|---|---|---|---|---|
0x00 |
0x00 |
0 |
Bank A Rom |
16 KB |
… |
… |
… |
||
0x3F |
0xFF |
16,383 |
||
0x40 |
0x00 |
16,384 |
Bank B RAM |
16 KB |
… |
… |
… |
||
0x7F |
0xFF |
32,767 |
||
0x80 |
0x00 |
32,768 |
Bank C RAM |
16 KB |
… |
… |
… |
||
0xBF |
0xFF |
49,151 |
||
0xC0 |
0x00 |
49,152 |
Bank D RAM |
16 KB |
… |
… |
… |
||
0xFF |
0xFF |
65,535 |
The first three memory banks (A, B, C) can be changed with a special instruction (TODO: Add instruction). Bank A is always a ROM though it could be system, cartrige or I/O ROM. This is because the program counter starts at 0x00 and must have executable code at boot. Bank B is not bankable because that is where the stack resides and banking that area of memory could cause errors.
The CPU must have the base 16 KB of ROM and 48 KB of RAM installed but the extended banks are optional.
The memory bank configuration is set via a register in the memory controller. The (Insert instruction here) instruction will write the contents of the A register to the memory bank register. Bank A is controlled by the lower 2 bits (0 and 1) of the register value and banks C and D are controlled by the next two bits (2 and 3) of the register value. As mentioned, bank B can can not be changed. This means there are four configurations for bank A, specifically the system ROM, BASIC ROM, cartrige ROM and IO ROM. Banks C and There are also four configurations for banks C and D.
A value of 0x00 is the default power on banking value. In this configuration there is no banking. The base 32 KB of ROM and 32 KB of RAM is used.
| Value | Bank A | Bank B | Bank C | Bank D |
|---|---|---|---|---|
0x00 |
ROM A:0 (Base A) |
ROM B:0 (BASE B) |
RAM C:0 (Base C) |
ROM D:0 (BASE D) |
0x01 |
ROM A:1 (BASIC) |
ROM B:0 (BASE B) |
RAM C:0 (Base C) |
ROM D:0 (BASE C) |
0x02 |
ROM A:2 (Cart) |
ROM B:0 (BASE B) |
RAM C:0 (Base C) |
ROM D:0 (BASE B) |
0x03 |
ROM A:3 (IO) |
ROM B:0 (BASE B) |
RAM C:0 (Base C) |
ROM D:0 (BASE B) |
0x00 |
ROM A:0 (Base A) |
ROM B:1 |
RAM C:1 |
ROM D:1 |
0x01 |
ROM A:1 (BASIC) |
ROM B:1 |
RAM C:1 |
ROM D:1 |
0x02 |
ROM A:2 (Cart) |
ROM B:1 |
RAM C:1 |
ROM D:1 |
0x03 |
ROM A:3 (IO) |
ROM B:1 |
RAM C:1 |
ROM D:1 |
0x00 |
ROM A:0 (Base A) |
ROM B:2 |
RAM C:2 |
ROM D:2 |
0x01 |
ROM A:1 (BASIC) |
ROM B:2 |
RAM C:2 |
ROM D:2 |
0x02 |
ROM A:2 (Cart) |
ROM B:2 |
RAM C:2 |
ROM D:2 |
0x03 |
ROM A:3 (IO) |
ROM B:2 |
RAM C:2 |
ROM D:2 |
0x00 |
ROM A:0 (Base A) |
ROM B:3 |
RAM C:3 |
ROM D:3 |
0x01 |
ROM A:1 (BASIC) |
ROM B:3 |
RAM C:3 |
ROM D:3 |
0x02 |
ROM A:2 (Cart) |
ROM B:3 |
RAM C:3 |
ROM D:3 |
0x03 |
ROM A:3 (IO) |
ROM B:3 |
RAM C:3 |
ROM D:3 |
Hardware
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ROM and RAM chips have 8-bit data width per chip. Thus needs two chips for 16 bit data bus width
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ram and rom interleaved between two chips
-
-
ROM
-
Uses AT28C64 which has 13 address lines and 8 data lines
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ROM code must be split abababab when programming
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A ROM set (A&B) with 13 address lines takes up 8 KB in the address space
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TODO: Figure out if mem module should use MDBus or DBUS???
-
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RAM
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Uses AS6C6264 which has 13 address lines and 8 data lines
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Similar chip splitting to the ROMs
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RAM read/write cycles take 55 - 65 ns which translate to about 15 MHz
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Appendix
Schematic
BOM
| Reference | Quantity | Value | Datasheet | Digikey | Price | Total |
|---|---|---|---|---|---|---|
C1 - C27 |
27 |
1uf |
||||
C41 - C44 |
4 |
10uf |
||||
D1 - D32 |
32 |
|||||
J2 - J3 |
2 |
1x24 pin header |
||||
RN1 - RN4 |
4 |
220R |
Y1221CT-ND |
|||
U1 - U4 |
4 |
AT28C64B-15PU |
||||
U5 - U16 |
12 |
AS6C6264-55PCN |
||||
U17 |
1 |
74HCT173 |
||||
U18 - U19 |
2 |
74HCT139 |
||||
U20 - U23 |
3 |
74HCT04 |
||||
U24 - U27 |
4 |
74HCT245 |
Notes
Breadboard controls (R-L)
-
RD
-
WR
-
MEM REQ
-
BANK